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ARMv9.3: what it is, how it works and what it does

ARMv9.3 (Armv9.3-A) is a revision of the 64-bit (AArch64) instruction set architecture in the Arm v9 family, incorporating the second-generation Scalable Matrix Extension (SME2) and serving as the basis for platforms built on C1 Ultra and C1 Pro cores.

Evidence-backed content 9 sources 15/09/2026
Encyclopedic article

ARMv9.3, formally designated Armv9.3-A, is a revision of the instruction set architecture (ISA) in the Arm v9 family, operating in AArch64 (64-bit) mode. The «-A» suffix denotes the Application Profile of the Arm architecture.

Principles and architecture

Armv9.3-A belongs to the Arm v9 line of architectures, which defines a 64-bit instruction set for general-purpose and high-performance processors. Revision 9.3 incorporates the SME2 (Scalable Matrix Extension 2) extension, a set of instructions targeting scalable matrix operations, relevant to advanced processing and scientific computing workloads.

The architecture is realised in specific cores; among them are Arm's C1 Ultra and C1 Pro cores, designed for platforms that adopt Armv9.3 as their instruction set foundation.

Applications and adoption

  • Mobile and high-performance platforms integrating C1 Ultra and C1 Pro cores built on Armv9.3.
  • Processor designs from manufacturers such as Samsung, which have stated the use of Armv9.3 and SME2 instructions in their architectures.
  • Systems where the SME2 extension enables acceleration of matrix operations for advanced processing inference and training.

Scope and limitations

Armv9.3-A is an architecture standard: it defines the behaviour of the instruction set, not a specific physical design. Its implementation depends on the cores and platforms that adopt it. The inclusion of SME2 as part of the instruction set implies that the hardware must support the corresponding execution units to exploit this extension.

Interpretation in a product

When a product or platform declares «Armv9.3-A (AArch64), SME2» as its instruction set, it indicates that:

  1. The processor operates exclusively in 64-bit mode (AArch64).
  2. The architecture level is revision 9.3 of the Arm Application Profile.
  3. The hardware includes support for second-generation Scalable Matrix Extension (SME2) instructions.

This combination places the product in the most recent generation of Arm architectures oriented toward performance and advanced processing workload acceleration.